The present invention is generally related to off-chip interconnects and, more particularly, is related to compliant off-chip interconnects.
The miniaturization of devices, high input/output (I/O) density, fast clock speed, good functionality and system integrity, low cost, and good reliability have driven advancements in the electronic industry. The rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push electronic packaging technology, in terms of size, performance, cost, and reliability. The minimum feature size in IC components will reach the scale of about 40 nanometers by 2001 according to International Technology Roadmap for Semiconductors (ITRS) 200 Update; requiring chip-to-substrate interconnect pitch in the range of few microns. There are no cost-effective and manufacturable chip-to-substrate interconnections that have such a fine pitch, and also able to accommodate the coefficient of thermal expansion (CTE) mismatch among different components without sacrificing reliability and performance. This has become a problem that will continue to limit the advances in the electronic industry.
Flip chips with solder bumps are being increasingly used in the electronic packaging industry, such packaging facilitates smaller chip size, higher I/O count, and shorter connection paths. Because of the larger CTE difference between the chip and substrate, underfill material is often added to reduce the significant shear strains in the solder bumps. Although underfill can greatly improve the flip chip interconnect reliability, there are still some challenges, such as the cost associated with dispensing the underfill as well as the time to cure the underfill. It should be noted that as the pitch size between solder bumps is reduced in the next-generation packaging, the height of solder bumps, and thus the gap also is reduced. Thus, the difficulty of underfill dispensing increases. Also, with reduced pitch, the reliability of the solder bumps is compromised.
Accommodation of CTE mismatch without underfill, fine pitch, high reliability, ease of fabrication, and low-cost are some of the challenges for next-generation interconnects from a thermo-mechanical perspective.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and/or inadequacies.
Briefly described, the present invention provides for electronic packages having new types of compliant off-chip interconnects. A representative electronic package includes a substrate and a free-standing compliant off-chip interconnect. The freestanding compliant off-chip interconnect includes a first free-standing arcuate structure that is substantially parallel to the substrate.
The present invention also provides methods for fabricating free-standing arcuate structure compliant off-chip interconnects. A representative method in accordance with the present invention includes the following steps: depositing an arcuate structure compliant off-chip interconnect material; and forming the free-standing arcuate structure compliant off-chip interconnect.
Other systems, methods, features, and advantages of the present invention will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims.